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    Analysis

    Beyond Moore's law: which hardware bets will pay off?

    Chipmakers are betting on two kinds of progress at once: incremental gains from new transistors, backside power and packaging, which are already in volume production, and radical alternatives such as neuromorphic and analog compute, which remain in research.[1][2][3] The main debates are which of these delivers the next big efficiency gains for AI, and how far vendor efficiency claims can be trusted.[4][5]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductorsComputing
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    The question

    Every route covered in this course promises more computing per watt. The open question for 2026-2030 is which routes will carry most of the gains for AI hardware, and on what evidence. This page separates sourced facts from interpretation and forecast.[6]

    Debate 1: incremental integration or new compute paradigms?

    Gate-all-around transistors and backside power are in volume production: TSMC’s N2 since the fourth quarter of 2025, and Intel’s 18A, with RibbonFET and PowerVia, in products since January 2026.[1][2][7] Intel claims 18A gives up to 15% better performance per watt than Intel 3.[8] Co-packaged optical switches reached production in 2026.[9] By contrast, the largest neuromorphic system, Hala Point, is a research prototype, and a leading analog in-memory attention design reported gains of up to four orders of magnitude in energy but needed small 64x64 arrays and an adaptation algorithm to run pre-trained models.[3][10][5]

    The evidence shows a gap in maturity, not necessarily in potential. Integration technologies deliver tens of percent per generation but ship at scale through existing fabs and software stacks. Radical approaches promise much larger factors on specific operations, yet each result so far comes with conditions (low precision, model adaptation, prototype scale) that make direct comparison with GPUs hard. The memory-wall analysis suggests both camps are attacking the same problem, data movement, from different ends.[6][11]

    Through about 2028, most delivered efficiency gains in data-center AI are likely to come from packaging, HBM integration and optics rather than from neuromorphic or analog chips, because those are already in production and capacity is expanding. Analog or spiking accelerators may first find use in narrower, power-constrained inference tasks. This forecast carries substantial uncertainty: a single demonstration of analog or spiking hardware running a production-scale model at competitive accuracy would change it.

    Debate 2: how fast will light replace copper?

    IEEE Spectrum reported that pluggable optics use about 10% of GPU compute power in AI data centers.[12] NVIDIA said Spectrum-X Ethernet Photonics was in production by May 2026, and Broadcom began sampling a 102.4 Tb/s CPO switch in October 2025, with a fourth generation in development.[9][13][14] Marvell paid about $3.25 billion for optical-interconnect startup Celestial AI in February 2026.[15] A UC Santa Barbara researcher told IEEE Spectrum that economics, not technology, had held CPO back.[16]

    Switches are the first beachhead because they concentrate the most optical ports in one place. The large acquisition and the startup products for optical I/O on processors suggest the industry expects optics to move closer to the GPU itself, where copper links are hardest to scale.[17][18] Serviceability of sealed-in optics remains a practical concern that public sources have not resolved.

    Optical links inside the GPU rack, not only between switches, are plausible within the next few product generations, but timing depends on laser reliability and packaging capacity; the bottleneck in CoWoS-class packaging, reported to persist through 2026, is a constraint.[19]

    Debate 3: how much should vendor numbers be trusted?

    Headline efficiency figures in this field mostly come from the companies or labs that built the hardware: NVIDIA’s 5x power efficiency for CPO, Broadcom’s roughly 70% optical power cut, Intel’s 15 TOPS/W for Hala Point and IBM’s 72.7x energy efficiency for NorthPole against a GPU.[4][20][21][22] TrendForce’s packaging figures rely on institutional investor estimates.[19]

    Vendor figures are not necessarily wrong, but baselines vary: “traditional transceivers”, “the next lowest latency GPU” and “conventional deep neural networks” are each chosen by the claimant. Readers should compare like with like and look for independent benchmarks or peer-reviewed results before treating any multiplier as general.

    Independent, workload-level comparisons are likely to become available first for co-packaged optics, as large operators deploy it, and later for neuromorphic and analog hardware. The tracker for this course follows such results.

    Competing views

    Integration wins

    The biggest near-term gains come from packaging, optics and better transistors inside the existing GPU-centric model: these are shipping, scale with existing fabs, and target the data-movement bottleneck directly.[9][23][6][7]

    New compute paradigms are needed

    Incremental scaling cannot keep up with AI's energy demand; computing in memory or with spiking neurons removes data movement altogether, and research prototypes already show orders-of-magnitude efficiency gains.[10][22][24][21]

    Show me the independent data

    Most headline efficiency numbers, for optics and new compute alike, come from vendors or single lab demonstrations on chosen workloads, with low precision or prototype scale; claims should be discounted until reproduced at scale.[20][5][3][16]

    Questions readers ask

    Is Moore's law over?

    Transistor density still improves, as TSMC's N2 and Intel's 18A show, but the power-density bargain that made chips faster each generation ended around 2005.[25][8][1]

    Will neuromorphic chips replace GPUs?

    There is no evidence of that yet. The largest neuromorphic system, Intel's Hala Point, is a research prototype.[3]

    Are co-packaged optics savings real?

    Vendors claim large savings, for example about 70% lower optical power (Broadcom) and 5x power efficiency (NVIDIA), but these are company figures.[20][4]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      TSMC's 2nm (N2) process started volume production in the fourth quarter of 2025, as planned. confirmedas of 2026-10-10

      • 2nm Technology · TSMC · 2nm Technology section (retrieved 2026-10-10)
    2. [2]

      Intel 18A, used for Panther Lake, combines RibbonFET transistors with PowerVia backside power delivery. confirmedas of 2025-10-09

    3. [3]

      Hala Point was initially deployed at Sandia National Laboratories and is a research prototype rather than a commercial product. confirmedas of 2024-04-17

    4. [4]

      NVIDIA claims Spectrum-X Ethernet Photonics delivers 5x better power efficiency and 5x longer AI uptime than networks using traditional transceivers. confirmedas of 2026-05-31

    5. [5]

      The analog attention design could not run pre-trained models directly because of gain-cell non-idealities, so it needed an adaptation algorithm, and its gain-cell arrays were limited to 64x64 to contain voltage (IR) drop. confirmedas of 2025-09-08

    6. [6]

      The same analysis argues that memory bandwidth, rather than compute, has become the primary bottleneck for AI workloads, especially when serving models. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    7. [7]

      Intel launched Core Ultra Series 3 (Panther Lake), the first compute platform built on Intel 18A, at CES on January 5, 2026, saying systems would be available that month. confirmedas of 2026-01-05

    8. [8]

      Intel says 18A delivers up to 15% better performance per watt and 30% better chip density than Intel 3, and calls it the first 2-nanometer-class node developed and manufactured in the United States. confirmedas of 2025-10-09

    9. [9]

      By May 31, 2026, NVIDIA said its Spectrum-X Ethernet Photonics co-packaged-optics switches with 200Gb/s SerDes were in production. confirmedas of 2026-05-31

    10. [10]

      A September 2025 Nature Computational Science paper reported an analog in-memory attention design that cut attention latency and energy by up to two and four orders of magnitude, respectively, compared with GPUs. confirmedas of 2025-09-08

    11. [11]

      IBM researchers describe the cost of conventional AI inference as the time and energy spent moving model weights between memory and processors. confirmedas of 2025-01-29

    12. [12]

      IEEE Spectrum reported that pluggable optical transceivers consume about 10% of total GPU compute power in AI data centers, more than half of it to drive lasers. reportedas of 2025-03-25

    13. [13]

      In October 2025 Broadcom began sampling Tomahawk 6-Davisson, its third-generation co-packaged-optics Ethernet switch with 102.4 Tb/s of capacity, to early-access customers. reportedas of 2025-10-08

    14. [14]

      Broadcom says a fourth-generation co-packaged-optics platform targeting 400 Gbps per channel is in development. reportedas of 2025-10-08· forecast

    15. [15]

      Marvell completed its roughly $3.25 billion acquisition of optical-interconnect startup Celestial AI on February 2, 2026. reportedas of 2026-02-02

    16. [16]

      A UC Santa Barbara co-packaged-optics researcher told IEEE Spectrum that NVIDIA would only adopt CPO once GPU-heavy data centers could no longer afford the power of pluggables. reportedas of 2025-03-25

    17. [17]

      Ayar Labs unveiled on March 31, 2025 an 8 Tbps TeraPHY optical I/O chiplet with a UCIe electrical interface, powered by a 16-wavelength light source. confirmedas of 2025-03-31

    18. [18]

      Lightmatter unveiled the Passage M1000 on March 31, 2025, a photonic interposer of more than 4,000 square millimetres offering 114 Tbps of optical bandwidth, built on GlobalFoundries' Fotonix platform. confirmedas of 2025-03-31

    19. [19]

      Institutional investors cited by Taiwan's Economic Daily News expected the CoWoS supply-demand gap to narrow from about 20% to about 10% by the end of 2026. reportedas of 2026-06-15· forecast

    20. [20]

      Broadcom says Tomahawk 6-Davisson cuts optical interconnect power by about 70% compared with pluggable transceivers. reportedas of 2025-10-08

    21. [21]

      Intel says Hala Point reaches 15 trillion 8-bit operations per second per watt when running conventional deep neural networks. confirmedas of 2024-04-17

    22. [22]

      IBM reported in September 2024 that NorthPole ran a 3-billion-parameter language model at under 1 millisecond per token with 72.7 times the energy efficiency of the next-lowest-latency GPU. confirmedas of 2024-09-26

    23. [23]

      TSMC's monthly CoWoS packaging capacity is reported to reach 120,000-140,000 wafers in 2026, with partner packaging firms adding 50,000-60,000. reportedas of 2026-06-15

    24. [24]

      The review's authors present neuromorphic computing as a response to AI's electricity consumption, which they say is projected to double by 2026. reportedas of 2025-01-23· interpretation

    25. [25]

      Dennard scaling broke down around 2005, creating a "power wall" that limited further increases in processor clock frequency. confirmedas of 2026-10-10

    Revision history (2)
    1. Page created.
    2. Corrected the analog attention limits and the Panther Lake availability claim to match their sources.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "Beyond Moore's law: which hardware bets will pay off?." ContentLora, updated Oct 10, 2026. https://contentlora.com/analysis/post-moore-hardware-debate

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