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    Next-gen computing hardware in 2026: a crash course

    Transistors no longer get cheaper, cooler and faster just by shrinking, so chipmakers now gain ground through new transistor shapes, power wiring on the back of the wafer, stacked chiplets, light-based links and brain- or memory-inspired processors.[1][2] As of October 2026, gate-all-around transistors and backside power are in volume production, and co-packaged optical switches are shipping.[3][4][5]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductorsComputing

    Why this field matters

    For about forty years, computers got faster mostly because the transistors inside chips kept shrinking. Smaller transistors used less power each, so more could be packed in without the chip overheating.[6] Around 2005 that bargain broke. Chips hit a “power wall”, and clock speeds stopped climbing.[1]

    Since then, progress has come from cleverer designs rather than shrinking alone. Today’s AI systems also run into a second wall: processors can calculate far faster than memory can feed them data.[7] “Next-gen computing hardware” is the set of ideas aimed at both walls.

    The end of Dennard scaling around 2005 forced a move to multi-core designs, then to dark silicon and heterogeneous accelerators such as GPUs.[1][8][2] For AI, a 2024 analysis found peak server FLOPS rising about 3.0x every two years against 1.6x for DRAM bandwidth and 1.4x for interconnect bandwidth, which makes data movement the main constraint.[7][9] The field therefore targets three things: energy per switch (transistor and power delivery), energy per bit moved (packaging and optics), and how much data has to move at all (in-memory and neuromorphic compute).

    The map: five sub-areas

    1. New transistors. Gate-all-around (GAA) transistors wrap the gate around stacked silicon sheets. Samsung began 3nm GAA production in 2022, TSMC’s N2 began volume production in late 2025, and Intel’s 18A uses its RibbonFET version.[10][3][11]
    2. Power from below. Backside power delivery moves power wires under the transistors, freeing the front for signals.[12] Intel ships it in 18A as PowerVia, and TSMC is adding it in A16.[4][13]
    3. Chiplets and advanced packaging. Big processors are now built from several smaller dies, or chiplets, joined in one package. Hybrid bonding stacks dies with direct copper connections.[14][15]
    4. Light instead of copper. Co-packaged optics puts optical engines inside the switch or processor package to cut the power used to move data.[16]
    5. New ways to compute. Neuromorphic chips imitate the brain’s spiking neurons, and analog in-memory computing does maths inside memory arrays so weights never move.[17][18]

    Key ideas to hold on to

    • Moving data costs more than computing on it. Much of a modern AI chip’s energy goes into shuttling numbers around, which is why packaging, memory and optics now matter as much as transistors.[18]
    • One chip is no longer one die. Splitting a design into chiplets improves yield, because a defect only ruins one small piece.[19]
    • Lab results are not products. Neuromorphic and analog chips show large efficiency gains in research, but Intel’s largest neuromorphic system is still a research prototype.[20]
    • Interconnect energy dominates. Pluggable optics alone were reported to use about 10% of GPU compute power in AI data centers, the main motivation for co-packaged optics.[21]
    • Packaging is a capacity bottleneck. TSMC’s CoWoS capacity was reported to reach 120,000-140,000 wafers a month in 2026, with demand still outrunning supply.[22][23]
    • Analog and spiking hardware trade precision for efficiency. A 2025 analog attention design reported up to four orders of magnitude lower attention energy than GPUs, but needed small arrays and hardware-aware model adaptation.[24][25]

    Who the main players are

    TSMC, Samsung and Intel all make gate-all-around transistors, and TSMC and Intel have both put backside power into their processes.[13][10][4] Belgium’s imec is the main shared research centre that maps what comes after nanosheets.[26][27] In optics, NVIDIA and Broadcom ship co-packaged switches, while Lightmatter and Ayar Labs build photonic interposers and optical chiplets; Marvell bought Celestial AI in 2026.[5][28][29][30][31] In brain-inspired and in-memory compute, Intel (Loihi 2, Hala Point) and IBM (NorthPole, phase-change analog chips) are the most visible.[32][33][34] The UCIe Consortium sets the open chiplet-to-chiplet interface standard.[35]

    Where the frontier is in October 2026

    Gate-all-around transistors are now the norm at the leading edge: Intel launched Core Ultra Series 3 on 18A in January 2026, and TSMC schedules N2P for the second half of 2026.[36][37] imec’s roadmap points to forksheet transistors and then stacked CFETs around the A7 node.[27] Co-packaged optics crossed into production in 2026.[5] Neuromorphic and analog in-memory computing remain mostly in research, with the open question being whether they can beat GPUs on real workloads at scale. The debate page at the end of this course sets out the competing views, and the tracker follows new milestones.[38][39]

    Questions readers ask

    Why can't chipmakers just keep shrinking transistors like before?

    Shrinking used to keep power density constant (Dennard scaling), but that broke down around 2005, creating a power wall that stopped clock speeds rising.[6][1]

    Are gate-all-around transistors in real products yet?

    Yes. TSMC's N2 entered volume production in late 2025, and Intel launched Core Ultra Series 3 laptops on Intel 18A in January 2026.[3][36]

    Is light replacing copper inside data centers?

    Partly. Co-packaged optical switches from NVIDIA were in production by May 2026, and Broadcom began sampling a 102.4 Tb/s CPO switch in October 2025.[5][28]

    What is the biggest bottleneck for AI hardware today?

    One widely cited analysis argues it is memory bandwidth, which has grown far slower than raw compute.[7][9]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      Dennard scaling broke down around 2005, creating a "power wall" that limited further increases in processor clock frequency. confirmedas of 2026-10-10

    2. [2]

      More recently, heterogeneous designs pair general-purpose cores with specialized accelerators such as GPUs to improve performance per watt. confirmedas of 2026-10-10

    3. [3]

      TSMC's 2nm (N2) process started volume production in the fourth quarter of 2025, as planned. confirmedas of 2026-10-10

      • 2nm Technology · TSMC · 2nm Technology section (retrieved 2026-10-10)
    4. [4]

      Intel 18A, used for Panther Lake, combines RibbonFET transistors with PowerVia backside power delivery. confirmedas of 2025-10-09

    5. [5]

      By May 31, 2026, NVIDIA said its Spectrum-X Ethernet Photonics co-packaged-optics switches with 200Gb/s SerDes were in production. confirmedas of 2026-05-31

    6. [6]

      For decades Dennard scaling kept chip power density roughly constant as transistors shrank, sustaining Moore's-law performance gains. confirmedas of 2026-10-10

    7. [7]

      A 2024 analysis found peak server hardware FLOPS grew about 3.0x every two years, while DRAM bandwidth grew about 1.6x and interconnect bandwidth about 1.4x over the same period. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    8. [8]

      Multi-core scaling hit its own limit, "dark silicon", where some cores must stay idle or slowed to remain within power and thermal budgets. confirmedas of 2026-10-10

    9. [9]

      The same analysis argues that memory bandwidth, rather than compute, has become the primary bottleneck for AI workloads, especially when serving models. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    10. [10]

      Samsung announced on June 30, 2022 that it had begun production on a 3nm process using gate-all-around transistors, calling it the world's first 3nm process with its MBCFET design. confirmedas of 2022-06-30

    11. [11]

      Intel describes RibbonFET, its gate-all-around transistor used in Intel 18A, as its first new transistor architecture in over a decade. confirmedas of 2025-10-09

    12. [12]

      Backside power delivery moves a chip's power wires below the transistors to the back of the wafer, leaving the front side for signal wiring. confirmedas of 2023-06-05

    13. [13]

      TSMC's A16 process combines nanosheet transistors with a backside power rail to improve logic density and performance. confirmedas of 2026-10-10

    14. [14]

      Chiplets are small, modular pieces of silicon, each with a specific function, that are combined into a larger system inside one package. confirmedas of 2025-04-11

    15. [15]

      Hybrid bonding joins two chips with dense, direct copper-to-copper connections instead of solder bumps; the copper pads are surrounded by insulating oxide and slightly recessed from its surface. confirmedas of 2024-08-11

    16. [16]

      In co-packaged optics, silicon optical-transceiver chiplets sit beside the switch chip inside one package, while the lasers, made from non-silicon materials, stay outside, shortening electrical paths and reducing components. confirmedas of 2025-03-25

    17. [17]

      Neuromorphic computing applies principles of neuroscience to computing systems to mimic the brain's structure and function. confirmedas of 2025-01-23

    18. [18]

      IBM researchers describe the cost of conventional AI inference as the time and energy spent moving model weights between memory and processors. confirmedas of 2025-01-29

    19. [19]

      Smaller dies yield better; the UCIe Consortium gives an example where a 1mm x 1mm die yields 99.9% but a 20mm x 20mm die yields 67%, and with chiplets only a flawed piece is discarded. confirmedas of 2025-04-11

    20. [20]

      Hala Point was initially deployed at Sandia National Laboratories and is a research prototype rather than a commercial product. confirmedas of 2024-04-17

    21. [21]

      IEEE Spectrum reported that pluggable optical transceivers consume about 10% of total GPU compute power in AI data centers, more than half of it to drive lasers. reportedas of 2025-03-25

    22. [22]

      TSMC's monthly CoWoS packaging capacity is reported to reach 120,000-140,000 wafers in 2026, with partner packaging firms adding 50,000-60,000. reportedas of 2026-06-15

    23. [23]

      Institutional investors cited by Taiwan's Economic Daily News expected the CoWoS supply-demand gap to narrow from about 20% to about 10% by the end of 2026. reportedas of 2026-06-15· forecast

    24. [24]

      A September 2025 Nature Computational Science paper reported an analog in-memory attention design that cut attention latency and energy by up to two and four orders of magnitude, respectively, compared with GPUs. confirmedas of 2025-09-08

    25. [25]

      The analog attention design could not run pre-trained models directly because of gain-cell non-idealities, so it needed an adaptation algorithm, and its gain-cell arrays were limited to 64x64 to contain voltage (IR) drop. confirmedas of 2025-09-08

    26. [26]

      imec describes itself as "the chip lab of the world" and works with all parts of the chip ecosystem, including more than 200 universities. confirmedas of 2026-10-10

    27. [27]

      imec's logic roadmap has the forksheet transistor extending nanosheets to the A10 node and monolithic CFET arriving at the A7 node. reportedas of 2026-02-26· forecast

    28. [28]

      In October 2025 Broadcom began sampling Tomahawk 6-Davisson, its third-generation co-packaged-optics Ethernet switch with 102.4 Tb/s of capacity, to early-access customers. reportedas of 2025-10-08

    29. [29]

      Lightmatter unveiled the Passage M1000 on March 31, 2025, a photonic interposer of more than 4,000 square millimetres offering 114 Tbps of optical bandwidth, built on GlobalFoundries' Fotonix platform. confirmedas of 2025-03-31

    30. [30]

      Ayar Labs unveiled on March 31, 2025 an 8 Tbps TeraPHY optical I/O chiplet with a UCIe electrical interface, powered by a 16-wavelength light source. confirmedas of 2025-03-31

    31. [31]

      Marvell completed its roughly $3.25 billion acquisition of optical-interconnect startup Celestial AI on February 2, 2026. reportedas of 2026-02-02

    32. [32]

      Intel's Hala Point, announced April 17, 2024, contains 1.15 billion neurons on 1,152 Loihi 2 processors made on the Intel 4 process. confirmedas of 2024-04-17

    33. [33]

      IBM's NorthPole inference chip is made on a 12nm process with 22 billion transistors in 795 square millimetres and keeps its memory on-chip. confirmedas of 2024-09-26

    34. [34]

      IBM's analog in-memory computing work stores neural-network weights in phase-change memory devices, whose conductivity changes as chalcogenide glass switches between crystalline and amorphous states. confirmedas of 2025-01-29

    35. [35]

      The UCIe 3.0 specification, released on August 5, 2025, raised chiplet link data rates from 32 GT/s to 48 GT/s and 64 GT/s. confirmedas of 2025-08-05

    36. [36]

      Intel launched Core Ultra Series 3 (Panther Lake), the first compute platform built on Intel 18A, at CES on January 5, 2026, saying systems would be available that month. confirmedas of 2026-01-05

    37. [37]

      TSMC schedules volume production of its enhanced N2P process for the second half of 2026. reportedas of 2026-10-10· forecast

    38. [38]

      A review by 23 researchers published in Nature on January 22, 2025 set out a roadmap for scaling neuromorphic computing. confirmedas of 2025-01-23

    39. [39]

      In January 2025 IBM Research described three studies on analog in-memory computing for transformer models - a 3D mixture-of-experts architecture featured in Nature Computational Science, a phase-change-memory edge accelerator presented at IEDM, and a transformer run on an analog chip, published in Nature Machine Intelligence. confirmedas of 2025-01-29

    Revision history (2)
    1. Page created.
    2. Corrected the analog attention limits, Panther Lake availability and IBM study descriptions to match their sources.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "Next-gen computing hardware in 2026: a crash course." ContentLora, updated Oct 10, 2026. https://contentlora.com/explain/computing-hardware

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