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    Gate-all-around (GAA) transistors

    Also known as GAA, GAAFET, nanosheet transistor, MBCFET, RibbonFET

    Gate-all-around (GAA) transistors wrap the gate on all sides of stacked silicon channels, giving tighter control of current than FinFETs. Samsung first produced them at 3nm in 2022, TSMC's N2 entered volume production in late 2025, and Intel's 18A uses its RibbonFET version.[1][2][3]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductors
    Key facts

    Gate-all-around (GAA) transistors are the transistor design used at the leading edge of chipmaking in 2026. The gate, which switches current on and off, wraps all the way around thin horizontal silicon channels, often called nanosheets. TSMC calls N2, which entered volume production in the fourth quarter of 2025, its first-generation nanosheet technology.[4][2]

    Why the industry switched

    The previous design, the FinFET, uses a vertical fin of silicon with the gate on three sides. Samsung describes its GAA design as overcoming FinFET performance limits: it lets chips run at a lower supply voltage, which saves power, while delivering more drive current, which improves speed.[5] Because power, not transistor count, has limited chip performance since the mid-2000s, gains in energy per switch are valuable.[6]

    Who makes them

    Samsung announced on June 30, 2022 that it had started production on a 3nm process with its Multi-Bridge-Channel FET (MBCFET), calling it the world’s first 3nm GAA process.[1] It said the first generation cut power by up to 45% and raised performance by 23% versus its 5nm process, and set targets of 50% lower power and 30% higher performance for a second generation.[7][8] Its first 2nm product is the Exynos 2600 smartphone processor, which Samsung describes as built on the industry’s first 2nm GAA process and listed in mass production in December 2025.[9] A June 2026 TechInsights teardown of a chip from a Galaxy S26+ confirmed it is made on Samsung’s 2nm SF2 process, with stacked nanosheet channels.[10] See samsung-electronics for the company’s wider foundry business.

    TSMC began volume production of N2, its first nanosheet node, in the fourth quarter of 2025, and schedules the enhanced N2P for the second half of 2026.[2][11] Its A16 process adds a backside power rail to nanosheets and is due to be production-ready in the second half of 2026.[12][13] After that, TSMC schedules A14 for volume production in 2028, claiming 10-15% more speed or 25-30% less power than N2 and over 20% higher logic density.[14] More on the company is at tsmc.

    Intel calls its version RibbonFET, its first new transistor architecture in over a decade.[3] RibbonFET is part of Intel 18A, which Intel says gives up to 15% better performance per watt and 30% higher density than Intel 3.[15] The first 18A products, Core Ultra Series 3 laptop processors, launched in January 2026, and 18A is made at Fab 52 in Arizona.[16][17]

    Intel’s next node, 14A, is where it plans to use High-NA EUV lithography from asml.[18] In January 2026 it had no committed external customer for 14A and said capacity spending would wait for customer commitments, expected from the second half of 2026.[19] In July 2026 Intel said it would begin 14A risk production for its own products in the second half of 2027 and had committed to a high-volume ramp in 2028; its finance chief said in August that 14A defect density was beating Intel’s internal target.[20][21] These are company statements reported by the trade press. See intel for the company’s foundry strategy.

    Pairing with backside power

    GAA rarely arrives alone. Intel’s 18A combines RibbonFET with PowerVia backside power delivery, and TSMC’s A16 pairs nanosheets with its own backside power rail.[22][12] The two changes address different limits: the transistor’s switching efficiency and the wiring that feeds it.[23]

    What comes next

    The research centre imec maps the steps after nanosheets. Its roadmap extends nanosheets with forksheet transistors to the A10 node, then moves to complementary FETs (CFETs) at the A7 node.[24] In a CFET, the n-type and p-type transistors are stacked on top of each other instead of side by side, shrinking the standard cell.[25] imec reported at IEDM 2025 that giving the n-type and p-type devices different channel orientations can raise drive current by up to 20%, a booster it expects the A3 node to need.[26] For how a transistor design becomes a working chip, see how chips are made.

    Independent comparisons of yield and density across the three manufacturers’ GAA processes are limited in public sources, so performance figures on this page are each company’s own.[15][7]

    Questions readers ask

    How is a GAA transistor different from a FinFET?

    Samsung says its GAA design overcomes FinFET performance limits by allowing a lower supply voltage and higher drive current.[5]

    Which chips use GAA transistors in 2026?

    Intel's Core Ultra Series 3 (Panther Lake) on 18A launched in January 2026, and TSMC's N2 has been in volume production since late 2025.[16][2]

    Has Samsung moved GAA to 2nm?

    Yes. Samsung lists its Exynos 2600 phone processor, built on its 2nm SF2 process, in mass production, and a TechInsights teardown confirmed the SF2 GAA process in a Galaxy S26+.[9][10]

    What comes after nanosheets?

    imec's roadmap extends nanosheets with forksheet transistors to the A10 node, then introduces stacked CFETs at the A7 node.[24]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      Samsung announced on June 30, 2022 that it had begun production on a 3nm process using gate-all-around transistors, calling it the world's first 3nm process with its MBCFET design. confirmedas of 2022-06-30

    2. [2]

      TSMC's 2nm (N2) process started volume production in the fourth quarter of 2025, as planned. confirmedas of 2026-10-10

      • 2nm Technology · TSMC · 2nm Technology section (retrieved 2026-10-10)
    3. [3]

      Intel describes RibbonFET, its gate-all-around transistor used in Intel 18A, as its first new transistor architecture in over a decade. confirmedas of 2025-10-09

    4. [4]

      N2 is TSMC's first process to use nanosheet (gate-all-around) transistors. confirmedas of 2026-10-10

    5. [5]

      Samsung describes its gate-all-around MBCFET as overcoming FinFET performance limits by allowing lower supply voltage and higher drive current. confirmedas of 2022-06-30

    6. [6]

      Dennard scaling broke down around 2005, creating a "power wall" that limited further increases in processor clock frequency. confirmedas of 2026-10-10

    7. [7]

      Samsung said its first-generation 3nm GAA process cut power by up to 45%, raised performance by 23% and reduced area by 16% compared with its 5nm process. confirmedas of 2022-06-30

    8. [8]

      In 2022 Samsung said its second-generation 3nm process would cut power by up to 50%, raise performance by 30% and reduce area by 35% compared with 5nm. confirmedas of 2022-06-30· forecast

    9. [9]

      Samsung's Exynos 2600 smartphone processor, which Samsung lists as built on the industry's first 2nm gate-all-around process, was listed in mass production in December 2025. confirmedas of 2025-12-19

    10. [10]

      A June 2026 TechInsights teardown of an Exynos 2600 from a Galaxy S26+ phone confirmed the die is made on Samsung's 2nm SF2 gate-all-around process, using stacked nanosheet channels in Samsung's MBCFET design. confirmedas of 2026-06-01

    11. [11]

      TSMC schedules volume production of its enhanced N2P process for the second half of 2026. reportedas of 2026-10-10· forecast

    12. [12]

      TSMC's A16 process combines nanosheet transistors with a backside power rail to improve logic density and performance. confirmedas of 2026-10-10

    13. [13]

      TSMC says A16 will offer 8-10% higher speed at the same voltage or 15-20% lower power at the same speed than N2P, with up to 1.10x chip density, and will be production-ready in the second half of 2026. confirmedas of 2026-10-10· forecast

      • 2nm Technology · TSMC · A16 Technology section (retrieved 2026-10-10)
      • 2nm Technology · TSMC · A16 Technology section (retrieved 2026-10-10)
    14. [14]

      TSMC schedules its A14 process, a full-node step achieved through dimensional scaling, for volume production in 2028, promising 10-15% more speed or 25-30% less power than N2 and more than 20% higher logic density. confirmedas of 2026-10-10· forecast

      • 2nm Technology · TSMC · A14 Technology section (retrieved 2026-10-10)
      • 2nm Technology · TSMC · A14 Technology section (retrieved 2026-10-10)
    15. [15]

      Intel says 18A delivers up to 15% better performance per watt and 30% better chip density than Intel 3, and calls it the first 2-nanometer-class node developed and manufactured in the United States. confirmedas of 2025-10-09

    16. [16]

      Intel launched Core Ultra Series 3 (Panther Lake), the first compute platform built on Intel 18A, at CES on January 5, 2026, saying systems would be available that month. confirmedas of 2026-01-05

    17. [17]

      Intel 18A chips are produced at Fab 52, Intel's fifth high-volume fab at its Ocotillo campus in Chandler, Arizona. confirmedas of 2025-10-09

    18. [18]

      Intel confirmed in January 2026 that High-NA EUV lithography is targeted at its 14A process. reportedas of 2026-01-23

    19. [19]

      In January 2026 Intel said it had no committed external customer for its 14A process yet, but that customers were evaluating its 0.5 process design kit and would begin making firm supplier decisions from the second half of 2026 into the first half of 2027. confirmedas of 2026-01-23

    20. [20]

      In July 2026 Intel said it remained on track for 14A risk production of its own products in the second half of 2027 and had decided to fully commit to a high-volume 14A ramp in 2028. reportedas of 2026-07-24· forecast

    21. [21]

      In August 2026 Intel's chief financial officer said 14A defect density was tracking better than Intel's target curve, though production remained about two years away. reportedas of 2026-08-28

    22. [22]

      Intel 18A, used for Panther Lake, combines RibbonFET transistors with PowerVia backside power delivery. confirmedas of 2025-10-09

    23. [23]

      Intel says power wires can take up to 20% of the front-side wiring area in a conventional chip. confirmedas of 2023-06-05

    24. [24]

      imec's logic roadmap has the forksheet transistor extending nanosheets to the A10 node and monolithic CFET arriving at the A7 node. reportedas of 2026-02-26· forecast

    25. [25]

      In a complementary FET (CFET), n-type and p-type transistors are stacked on top of each other, so the gap between them no longer sets standard-cell height. confirmedas of 2026-02-26

    26. [26]

      imec's design study for monolithic CFETs, presented at IEDM 2025, found that giving n- and p-type devices different channel orientations can raise drive current by up to 20%, a booster it expects the A3 node to need. confirmedas of 2026-02-26

    Revision history (2)
    1. Page created.
    2. Added Samsung SF2 (Exynos 2600), Intel 14A and TSMC A14 roadmap status; corrected the imec CFET result and the Panther Lake availability claim.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "Gate-all-around (GAA) transistors." ContentLora, updated Oct 10, 2026. https://contentlora.com/wiki/gate-all-around-transistors

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