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    Chiplets and advanced packaging

    Also known as chiplet, multi-die, 2.5D packaging, 3D packaging, CoWoS, Foveros, UCIe

    Chiplets are small dies, each with a specific function, combined into one package to act as a single processor.[1] They get around the maximum die size lithography can print, improve yield, and let designers mix process nodes; in 2026, packaging capacity for the largest AI chips is still a reported bottleneck.[2][3][4]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductors
    Key facts

    A chiplet is a small piece of silicon with a specific function, designed to be combined with other chiplets in one package so that together they act as a single processor.[1] Large processors such as NVIDIA’s Blackwell GPU and Intel’s Panther Lake are built this way, using advanced packaging such as TSMC’s CoWoS and Intel’s Foveros.[5][6]

    Why chiplets

    Making one huge chip is risky: a single speck of dust can ruin it. The UCIe Consortium gives an example where a tiny 1mm die comes out working 99.9% of the time but a 20mm die only 67% of the time. Build the same processor from several small chiplets, and a defect only costs you one small piece.[3] There is also a hard size limit: lithography machines can only print a die up to a certain area, the reticle limit, so the biggest AI processors have no choice but to use several dies.[2]

    Three economic drivers dominate. Yield falls steeply with die area, so disaggregation recovers good silicon.[3] Designs that need more transistors than one reticle-limited die must be split.[2] And because leading-edge wafers are expensive, only performance-critical blocks need the newest node, while analog, RF or I/O can stay on mature nodes.[7] The trade-off is die-to-die interconnect: advanced 2.5D packages commonly use 25-55 µm pitches, and stacked chiplets can go as low as 1 µm though 5-25 µm is more common, far coarser than on-die wiring.[8]

    Packaging technologies

    2.5D packaging places dies side by side on a silicon interposer. As of 2024, NVIDIA’s Blackwell GPU used TSMC’s CoWoS to combine more than three reticles’ worth of silicon with eight high-bandwidth memory (HBM) stacks.[5] TSMC projected in 2024 a 2027 wafer-scale version with more than 40 reticles of silicon and room for over 60 HBM stacks.[9]

    3D packaging stacks dies on top of each other. Intel’s Foveros stacks and integrates multiple chiplets and is used in Panther Lake.[6] The densest 3D links use hybrid bonding, which joins dies with direct copper connections.[10]

    The UCIe standard

    For chiplets from different vendors to work together, they need a common interface. The Universal Chiplet Interconnect Express (UCIe) standard aims to let dies made by different companies at different foundries be assembled into working packages.[11] UCIe 3.0, released on August 5, 2025, raised data rates from 32 GT/s to 48 and 64 GT/s.[12] Optical chiplets are adopting it too: Ayar Labs’ TeraPHY optical I/O chiplet uses a UCIe electrical interface.[13]

    The packaging bottleneck

    Demand for advanced packaging has outrun supply since the AI boom. TSMC’s CoWoS capacity was reported to reach 120,000-140,000 wafers a month in 2026, with partner packaging houses adding 50,000-60,000.[14] Even so, institutional investors cited by Taiwan’s Economic Daily News expected a supply shortfall of about 10% at the end of 2026, down from about 20%.[4] TSMC forecast CoWoS capacity growth of more than 80% a year from 2022 to 2027.[15]

    Questions readers ask

    Why split a processor into chiplets?

    Smaller dies have higher yields, so a defect ruins only one small piece, and designs can exceed the maximum die size a lithography tool can print.[3][2]

    What is UCIe?

    An open standard for chiplet-to-chiplet links, meant to let dies from different companies and foundries work in one package. Version 3.0 (August 2025) supports up to 64 GT/s.[11][12]

    Is advanced packaging still a bottleneck in 2026?

    Reportedly yes. CoWoS demand was expected to exceed supply by about 10% at the end of 2026, down from about 20%.[4]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      Chiplets are small, modular pieces of silicon, each with a specific function, that are combined into a larger system inside one package. confirmedas of 2025-04-11

    2. [2]

      Chiplets let designers exceed the reticle limit, the maximum die size a lithography tool can pattern, which matters as AI chips demand more transistors. confirmedas of 2025-04-11

    3. [3]

      Smaller dies yield better; the UCIe Consortium gives an example where a 1mm x 1mm die yields 99.9% but a 20mm x 20mm die yields 67%, and with chiplets only a flawed piece is discarded. confirmedas of 2025-04-11

    4. [4]

      Institutional investors cited by Taiwan's Economic Daily News expected the CoWoS supply-demand gap to narrow from about 20% to about 10% by the end of 2026. reportedas of 2026-06-15· forecast

    5. [5]

      As of 2024, NVIDIA's Blackwell GPU used TSMC's CoWoS packaging to combine more than three reticles' worth of silicon with eight HBM memory stacks. confirmedas of 2024-04-30

    6. [6]

      Intel's Foveros is an advanced packaging and 3D stacking technology that integrates multiple chiplets into one system-on-chip, and Panther Lake uses it. confirmedas of 2025-10-09

    7. [7]

      Chiplets allow only performance-critical parts of a design to move to costly leading-edge nodes while other functions, such as RF and analog, stay on older nodes. confirmedas of 2025-04-11

    8. [8]

      According to the UCIe Consortium, standard packages connect chiplets at 100-150 micrometre pitches and advanced packages at 25-55 micrometres, while stacked chiplets can connect at pitches as low as 1 micrometre, with 5-25 micrometres currently more common. confirmedas of 2025-04-11

    9. [9]

      In 2024 TSMC projected a 2027 wafer-scale System-on-Wafer package with more than 40 reticles' worth of silicon and room for more than 60 HBM stacks. reportedas of 2024-04-30· forecast

    10. [10]

      Hybrid bonding joins two chips with dense, direct copper-to-copper connections instead of solder bumps; the copper pads are surrounded by insulating oxide and slightly recessed from its surface. confirmedas of 2024-08-11

    11. [11]

      The UCIe standard aims to let chiplets from different companies, made at different foundries, be assembled into working packages. confirmedas of 2025-08-05

    12. [12]

      The UCIe 3.0 specification, released on August 5, 2025, raised chiplet link data rates from 32 GT/s to 48 GT/s and 64 GT/s. confirmedas of 2025-08-05

    13. [13]

      Ayar Labs unveiled on March 31, 2025 an 8 Tbps TeraPHY optical I/O chiplet with a UCIe electrical interface, powered by a 16-wavelength light source. confirmedas of 2025-03-31

    14. [14]

      TSMC's monthly CoWoS packaging capacity is reported to reach 120,000-140,000 wafers in 2026, with partner packaging firms adding 50,000-60,000. reportedas of 2026-06-15

    15. [15]

      TSMC forecast in May 2026 that its CoWoS capacity will grow at a compound annual rate of more than 80% from 2022 to 2027. reportedas of 2026-06-15· forecast

    16. [16]

      Hybrid bonding is used in AMD processors and AI accelerators, in camera image sensors, and is being applied to high-bandwidth memory stacks. confirmedas of 2024-08-11

    Revision history (2)
    1. Page created.
    2. Corrected the stacked-chiplet pitch range to match the UCIe source.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "Chiplets and advanced packaging." ContentLora, updated Oct 10, 2026. https://contentlora.com/wiki/chiplets

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