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    Why chip scaling slowed, and what replaced it

    Shrinking transistors once kept chip power density constant, so each generation could run faster without overheating.[1] That stopped around 2005, and since then gains have come from more cores, specialized accelerators, and new transistor, packaging and power-delivery technology.[2][3]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductorsComputing

    The old bargain

    A transistor is a tiny switch. For decades, each new generation of chips made these switches smaller. The happy side effect was that smaller switches also needed less power, so a chip with twice as many transistors did not get twice as hot. Engineers call this pattern Dennard scaling.[1]

    Dennard scaling held that as feature sizes shrink, supply voltage and current shrink with them, so power density stays roughly constant. Combined with Moore’s-law density gains, it delivered higher clock frequencies essentially for free each generation.[1]

    The power wall

    Around 2005 the bargain broke. Transistors kept shrinking, but their power use stopped falling fast enough. Chips could no longer be made faster simply by raising the clock speed without overheating. This limit is called the power wall.[2]

    Once voltage could no longer scale with feature size, power density rose with each node. The result was the “power wall” of the mid-2000s, which capped clock frequencies.[2] Designers turned to parallelism instead.[4]

    Multi-core, dark silicon and accelerators

    The first response was to put several slower cores on one chip instead of one very fast core.[4] That too ran into limits: with many cores, the chip cannot power all of them at full speed at once, so some must sit idle or run slowly. This is called “dark silicon”.[5] The next response was specialization: pairing general-purpose cores with accelerators such as GPUs that do particular jobs, like the maths behind AI, far more efficiently per watt.[3]

    What the industry does now

    Since shrinking alone no longer delivers big wins, chipmakers attack the problem from several sides at once:

    • Better switches. New transistor shapes, called gate-all-around, control current more tightly. TSMC began making them in volume in late 2025.[6][7]
    • Better wiring. Moving power wires to the back of the chip, called backside power delivery, frees space for signals.[8]
    • Better assembly. Building one processor from several smaller chiplets avoids the cost of one giant, defect-prone die.[9]

    Post-Dennard gains now come from a stack of techniques. At the device level, gate-all-around nanosheets replace FinFETs; Samsung says its MBCFET lowers supply voltage and raises drive current versus FinFET.[10] At the interconnect level, backside power reclaims front-side routing: Intel says power wires can take up to 20% of front-side area.[11] At the system level, chiplets get around the reticle limit and let designers mix process nodes.[12][13] Each step is incremental; none restores the free frequency scaling of the Dennard era.

    Why it matters for AI

    AI workloads made the slowdown more urgent. Peak compute has outgrown memory and interconnect bandwidth, so moving data has become the main limit.[14] The next page in this course, on the memory wall, explains that second problem.[15]

    Questions readers ask

    What was Dennard scaling?

    The pattern in which shrinking transistors kept a chip's power density roughly constant, letting chips get faster each generation without running hotter.[1]

    When did it end?

    Around 2005, when a power wall stopped further clock-frequency increases.[2]

    What is dark silicon?

    The situation where some cores on a chip must stay idle or slowed to remain within power and thermal limits.[5]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      For decades Dennard scaling kept chip power density roughly constant as transistors shrank, sustaining Moore's-law performance gains. confirmedas of 2026-10-10

    2. [2]

      Dennard scaling broke down around 2005, creating a "power wall" that limited further increases in processor clock frequency. confirmedas of 2026-10-10

    3. [3]

      More recently, heterogeneous designs pair general-purpose cores with specialized accelerators such as GPUs to improve performance per watt. confirmedas of 2026-10-10

    4. [4]

      After the power wall, chip designers shifted to multi-core processors that spread work across several lower-frequency cores. confirmedas of 2026-10-10

    5. [5]

      Multi-core scaling hit its own limit, "dark silicon", where some cores must stay idle or slowed to remain within power and thermal budgets. confirmedas of 2026-10-10

    6. [6]

      TSMC's 2nm (N2) process started volume production in the fourth quarter of 2025, as planned. confirmedas of 2026-10-10

      • 2nm Technology · TSMC · 2nm Technology section (retrieved 2026-10-10)
    7. [7]

      N2 is TSMC's first process to use nanosheet (gate-all-around) transistors. confirmedas of 2026-10-10

    8. [8]

      Backside power delivery moves a chip's power wires below the transistors to the back of the wafer, leaving the front side for signal wiring. confirmedas of 2023-06-05

    9. [9]

      Smaller dies yield better; the UCIe Consortium gives an example where a 1mm x 1mm die yields 99.9% but a 20mm x 20mm die yields 67%, and with chiplets only a flawed piece is discarded. confirmedas of 2025-04-11

    10. [10]

      Samsung describes its gate-all-around MBCFET as overcoming FinFET performance limits by allowing lower supply voltage and higher drive current. confirmedas of 2022-06-30

    11. [11]

      Intel says power wires can take up to 20% of the front-side wiring area in a conventional chip. confirmedas of 2023-06-05

    12. [12]

      Chiplets let designers exceed the reticle limit, the maximum die size a lithography tool can pattern, which matters as AI chips demand more transistors. confirmedas of 2025-04-11

    13. [13]

      Chiplets allow only performance-critical parts of a design to move to costly leading-edge nodes while other functions, such as RF and analog, stay on older nodes. confirmedas of 2025-04-11

    14. [14]

      A 2024 analysis found peak server hardware FLOPS grew about 3.0x every two years, while DRAM bandwidth grew about 1.6x and interconnect bandwidth about 1.4x over the same period. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    15. [15]

      The same analysis argues that memory bandwidth, rather than compute, has become the primary bottleneck for AI workloads, especially when serving models. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    Revision history (1)
    1. Page created.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "Why chip scaling slowed, and what replaced it." ContentLora, updated Oct 10, 2026. https://contentlora.com/explain/why-chip-scaling-slowed

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