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    organization

    imec

    Also known as Interuniversity Microelectronics Centre, IMEC

    imec is a semiconductor research centre founded in 1984 and headquartered in Leuven, Belgium, that calls itself "the chip lab of the world".[1][2] Its logic roadmap, published openly, sets expectations for the transistors that follow today's nanosheets, with stacked CFETs expected around the A7 node.[3]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductors
    Key facts

    imec is a research centre for semiconductor technology, founded in 1984 and headquartered in Leuven, Belgium.[1] It employs about 6,500 scientists, engineers and other staff from more than 100 countries.[4] It matters for next-generation hardware because it publishes research and roadmaps on future transistors and chip stacking.[3][5]

    What it does

    imec describes itself as “the chip lab of the world” and works across the semiconductor ecosystem, including with more than 200 universities.[2] It calls itself the world’s largest independent research centre for nanoelectronics and digital technology and says it works with companies in a neutral, open innovation model.[6] Its facilities include a 3.5 billion euro 300mm pilot line, and it hosts the NanoIC pilot line, aligned with the EU Chips Act, for work beyond 2nm.[7]

    The logic roadmap

    imec’s best-known output is its logic technology roadmap, which sets out the transistor architectures it expects at each future node. In its February 2026 update, imec places the forksheet transistor as the step that extends nanosheet-based logic to the A10 node, with monolithic complementary FETs (CFETs) taking over at A7.[3] In a CFET, n-type and p-type transistors are stacked vertically instead of side by side, so the space between them no longer sets the height of a standard logic cell.[8] At IEDM 2024 imec showed a working monolithic CFET with a direct backside contact to the bottom transistor, and proposed a double-row CFET cell for A7.[9] A design study presented at IEDM 2025 found that giving the n- and p-type devices different channel orientations can raise drive current by up to 20%, a booster imec expects the A3 node to need.[10] This is the path that follows today’s gate-all-around transistors.

    Chip stacking and packaging

    imec also does research on hybrid bonding. It has demonstrated wafer-to-wafer bonding with a 400-nanometre pitch and chip-on-wafer bonding at 2 micrometres, far finer than the roughly 9-micrometre pitch in production parts as of 2024.[5][11] The same push toward vertical structures links its packaging and transistor research: both stack devices rather than spreading them out.[8][12]

    Where the roadmap starts from

    The roadmap builds on transistors already in production. Samsung began making gate-all-around transistors at 3nm in 2022, TSMC’s N2 nanosheet process entered volume production in the fourth quarter of 2025, and Intel’s 18A, with RibbonFET transistors, shipped in laptops from January 2026.[13][14][15] Manufacturers have published their own next steps: TSMC schedules A14 for 2028, Samsung has moved to 2nm with SF2, and Intel plans 14A for a 2028 volume ramp.[16][17][18] imec’s forksheet and CFET steps describe how that nanosheet generation could be extended and then replaced.[3] Stacking transistors vertically is a response to the same pressure that drives the rest of this field: since Dennard scaling ended around 2005, density and efficiency gains have had to come from new structures rather than simple shrinking.[19][8]

    Why its roadmap matters

    imec’s roadmap is a widely used public reference for what may follow nanosheets, but it is a research forecast, not a commitment by any manufacturer; actual timing depends on TSMC, Samsung and Intel.[3]

    Questions readers ask

    What is imec?

    A semiconductor research centre founded in 1984 in Leuven, Belgium, employing about 6,500 people from more than 100 countries.[1][4]

    What does imec's roadmap say comes after nanosheet transistors?

    Forksheet transistors extend nanosheets to the A10 node, and monolithic CFETs, which stack n- and p-type transistors, arrive at the A7 node.[3][8]

    What has imec shown in chip stacking?

    Wafer-to-wafer hybrid bonding at a 400-nanometre pitch.[5]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      imec, a semiconductor research centre headquartered in Leuven, Belgium, was founded in 1984. confirmedas of 2026-10-10

    2. [2]

      imec describes itself as "the chip lab of the world" and works with all parts of the chip ecosystem, including more than 200 universities. confirmedas of 2026-10-10

    3. [3]

      imec's logic roadmap has the forksheet transistor extending nanosheets to the A10 node and monolithic CFET arriving at the A7 node. reportedas of 2026-02-26· forecast

    4. [4]

      imec says it employs about 6,500 scientists, engineers and innovators from more than 100 countries. confirmedas of 2026-10-10

    5. [5]

      imec has demonstrated wafer-to-wafer hybrid bonding with a 400-nanometre pitch, and 2-micrometre pitch for chip-on-wafer bonding. confirmedas of 2024-08-11

    6. [6]

      imec describes itself as the world's largest independent research and innovation centre for nanoelectronics and digital technology, working with industry in a neutral, open innovation model. confirmedas of 2026-10-10

    7. [7]

      imec says its facilities include a 3.5 billion euro 300mm semiconductor pilot line, and it hosts the EU Chips Act-aligned NanoIC pilot line for beyond-2nm work. confirmedas of 2026-10-10

    8. [8]

      In a complementary FET (CFET), n-type and p-type transistors are stacked on top of each other, so the gap between them no longer sets standard-cell height. confirmedas of 2026-02-26

    9. [9]

      imec demonstrated a functional monolithic CFET with a direct backside contact to the bottom pMOS device at IEDM 2024, and proposed a double-row CFET standard cell for the A7 node. confirmedas of 2026-02-26

    10. [10]

      imec's design study for monolithic CFETs, presented at IEDM 2025, found that giving n- and p-type devices different channel orientations can raise drive current by up to 20%, a booster it expects the A3 node to need. confirmedas of 2026-02-26

    11. [11]

      As of 2024, hybrid-bonded 3D chips in production had connections about 9 micrometres apart, versus tens of micrometres for the solder microbumps they replace. confirmedas of 2024-08-11

    12. [12]

      Hybrid bonding joins two chips with dense, direct copper-to-copper connections instead of solder bumps; the copper pads are surrounded by insulating oxide and slightly recessed from its surface. confirmedas of 2024-08-11

    13. [13]

      Samsung announced on June 30, 2022 that it had begun production on a 3nm process using gate-all-around transistors, calling it the world's first 3nm process with its MBCFET design. confirmedas of 2022-06-30

    14. [14]

      TSMC's 2nm (N2) process started volume production in the fourth quarter of 2025, as planned. confirmedas of 2026-10-10

      • 2nm Technology · TSMC · 2nm Technology section (retrieved 2026-10-10)
    15. [15]

      Intel launched Core Ultra Series 3 (Panther Lake), the first compute platform built on Intel 18A, at CES on January 5, 2026, saying systems would be available that month. confirmedas of 2026-01-05

    16. [16]

      TSMC schedules its A14 process, a full-node step achieved through dimensional scaling, for volume production in 2028, promising 10-15% more speed or 25-30% less power than N2 and more than 20% higher logic density. confirmedas of 2026-10-10· forecast

      • 2nm Technology · TSMC · A14 Technology section (retrieved 2026-10-10)
      • 2nm Technology · TSMC · A14 Technology section (retrieved 2026-10-10)
    17. [17]

      Samsung's Exynos 2600 smartphone processor, which Samsung lists as built on the industry's first 2nm gate-all-around process, was listed in mass production in December 2025. confirmedas of 2025-12-19

    18. [18]

      In July 2026 Intel said it remained on track for 14A risk production of its own products in the second half of 2027 and had decided to fully commit to a high-volume 14A ramp in 2028. reportedas of 2026-07-24· forecast

    19. [19]

      Dennard scaling broke down around 2005, creating a "power wall" that limited further increases in processor clock frequency. confirmedas of 2026-10-10

    Revision history (2)
    1. Page created.
    2. Corrected the IEDM 2025 CFET result (channel orientation, not wafer bonding); added imec's pilot lines, operating model and mCFET backside-contact work.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "imec." ContentLora, updated Oct 10, 2026. https://contentlora.com/wiki/imec

    Spotted an error? Suggest a correction or emailcorrections@contentlora.com.

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