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    Backside power delivery

    Also known as BSPD, backside power, PowerVia, backside power rail

    Backside power delivery moves a chip's power wires from the crowded top layers to the back of the wafer, below the transistors, leaving the front for signals.[1] Intel's 18A, in products since January 2026, uses its PowerVia version, and TSMC's A16 adds a backside power rail to nanosheet transistors.[2][3]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductors
    Key facts

    Backside power delivery is a change to how electricity reaches a chip’s transistors. In conventional chips, power and signal wires share a stack of metal layers built on top of the transistors. Backside power moves the power wires underneath, to the back of the wafer, so the transistors sit between two wiring networks.[1]

    The problem it solves

    In a conventional chip, the transistors sit at the bottom and all the wiring is built above them. Intel says power wires can take up to 20% of that front-side wiring space.[4] As transistors shrink, that congestion makes it harder to route signals and to deliver stable voltage.[1]

    How it works

    Picture a building where water pipes and phone cables run through the same narrow ceiling space. Backside power moves the pipes under the floor. The ceiling is then free for cables, and the water arrives with less loss.[1]

    Power reaches the transistor layer from below rather than through the front-side metal stack. Freed front-side routing allows denser cell placement; Intel’s 2023 Blue Sky Creek E-core test chip with PowerVia, showed more than 5% frequency improvement and more than 90% cell density.[5] TSMC’s A16 uses a backside power rail with nanosheet transistors, which it says improves logic density and performance.[3]

    Who uses it

    Intel announced PowerVia in 2023 and said it would be the industry’s first implementation of backside power, with foundry customers gaining access in Intel 18A.[6] Intel 18A combines PowerVia with RibbonFET gate-all-around transistors, and its first products, Core Ultra Series 3 laptop processors, launched on January 5, 2026.[2][7] The Xeon 6+ server processor, code-named Clearwater Forest, is also built on 18A.[8]

    TSMC describes A16 as combining nanosheet transistors with a backside power rail for better logic density and performance.[3] It says the rail dedicates front-side routing to signals and reduces voltage (IR) drop, and that its backside contact scheme keeps the gate density and layout footprint of front-side designs.[9] Against its N2P process, TSMC claims A16 gives 8-10% more speed at the same voltage or 15-20% less power at the same speed, with up to 1.10x chip density, and says A16 will be production-ready in the second half of 2026.[10] It positions A16 for high-performance computing chips with complex signal routes and dense power networks, and schedules A12, a second-generation backside power process, for 2029.[10][11] Its mainstream A14 node, due in 2028, is described in terms of dimensional scaling rather than backside power.[12]

    Intel plans 14A as its next node after 18A, with risk production for its own products in the second half of 2027 and a volume ramp in 2028.[13]

    Backside access also appears in research on future transistors: imec demonstrated a functional monolithic CFET with a direct backside contact to the bottom transistor at IEDM 2024.[14] For where power wiring fits among the steps of making a chip, see how chips are made.

    Open questions

    Public data on how backside power affects manufacturing yield and cost is limited; the performance figures available are Intel’s own test-chip results.[5] Whether backside power becomes standard for all leading-edge designs, or mainly for high-power AI and server chips, is not yet clear from public sources. For now TSMC positions A16 for high-performance computing products and offers A14, without a stated backside power rail, as its mainstream 2028 node.[10][12]

    Questions readers ask

    Why put power wires on the back of the chip?

    Power wires can take up to 20% of front-side wiring area; moving them to the back frees that space for signals.[4][1]

    Is backside power in shipping products?

    Yes. Intel 18A, which includes PowerVia, is used in Core Ultra Series 3 processors launched in January 2026.[2][7]

    When does TSMC's backside power arrive?

    TSMC says A16, its first process with a backside power rail, will be production-ready in the second half of 2026, and schedules a second-generation version, A12, for 2029.[10][11]

    What gains did Intel measure?

    Its 2023 Blue Sky Creek test chip showed more than 5% frequency improvement and more than 90% cell density.[5]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      Backside power delivery moves a chip's power wires below the transistors to the back of the wafer, leaving the front side for signal wiring. confirmedas of 2023-06-05

    2. [2]

      Intel 18A, used for Panther Lake, combines RibbonFET transistors with PowerVia backside power delivery. confirmedas of 2025-10-09

    3. [3]

      TSMC's A16 process combines nanosheet transistors with a backside power rail to improve logic density and performance. confirmedas of 2026-10-10

    4. [4]

      Intel says power wires can take up to 20% of the front-side wiring area in a conventional chip. confirmedas of 2023-06-05

    5. [5]

      In 2023 Intel reported that an E-core test chip with PowerVia, called Blue Sky Creek, showed more than 5% frequency improvement and more than 90% cell density. confirmedas of 2023-06-05

    6. [6]

      In 2023 Intel said PowerVia would be the industry's first implementation of backside power delivery, and that foundry customers would get it in Intel 18A. confirmedas of 2023-06-05

    7. [7]

      Intel launched Core Ultra Series 3 (Panther Lake), the first compute platform built on Intel 18A, at CES on January 5, 2026, saying systems would be available that month. confirmedas of 2026-01-05

    8. [8]

      Intel's Clearwater Forest server processor, branded Xeon 6+, is also built on Intel 18A. confirmedas of 2025-10-09

    9. [9]

      TSMC says A16's backside power rail frees front-side wiring for signals, reduces voltage (IR) drop, and uses a backside contact scheme that keeps gate density and layout footprint. confirmedas of 2026-10-10

      • 2nm Technology · TSMC · A16 Technology section (retrieved 2026-10-10)
      • 2nm Technology · TSMC · A16 Technology section (retrieved 2026-10-10)
    10. [10]

      TSMC says A16 will offer 8-10% higher speed at the same voltage or 15-20% lower power at the same speed than N2P, with up to 1.10x chip density, and will be production-ready in the second half of 2026. confirmedas of 2026-10-10· forecast

      • 2nm Technology · TSMC · A16 Technology section (retrieved 2026-10-10)
      • 2nm Technology · TSMC · A16 Technology section (retrieved 2026-10-10)
    11. [11]

      TSMC describes A12 as its second-generation backside power rail process with nanosheet transistors, scheduled for volume production in 2029. confirmedas of 2026-10-10· forecast

      • 2nm Technology · TSMC · A12 Technology section (retrieved 2026-10-10)
      • 2nm Technology · TSMC · A12 Technology section (retrieved 2026-10-10)
    12. [12]

      TSMC schedules its A14 process, a full-node step achieved through dimensional scaling, for volume production in 2028, promising 10-15% more speed or 25-30% less power than N2 and more than 20% higher logic density. confirmedas of 2026-10-10· forecast

      • 2nm Technology · TSMC · A14 Technology section (retrieved 2026-10-10)
      • 2nm Technology · TSMC · A14 Technology section (retrieved 2026-10-10)
    13. [13]

      In July 2026 Intel said it remained on track for 14A risk production of its own products in the second half of 2027 and had decided to fully commit to a high-volume 14A ramp in 2028. reportedas of 2026-07-24· forecast

    14. [14]

      imec demonstrated a functional monolithic CFET with a direct backside contact to the bottom pMOS device at IEDM 2024, and proposed a double-row CFET standard cell for the A7 node. confirmedas of 2026-02-26

    Revision history (2)
    1. Page created.
    2. Added TSMC's A16 production timing and figures, A12 second-generation plans, and imec's backside-contact CFET work; corrected the Panther Lake availability claim.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "Backside power delivery." ContentLora, updated Oct 10, 2026. https://contentlora.com/wiki/backside-power-delivery

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