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    How advanced chips are made

    An advanced chip is designed in software, printed layer by layer onto a silicon wafer in a fab, then cut out and packaged.[1][2] The core printing step, lithography, uses ultraviolet light, and the finest layers now use extreme ultraviolet (EUV) light at 13.5 nm.[3]

    Editor reviewedUpdated SemiconductorsScience

    Making an advanced chip takes four main stages: design, wafer fabrication, lithography and packaging. Lithography happens inside wafer fabrication, but it gets its own section here because it sets how small features can be.[4] Choose a reading level in each section.

    Design

    Engineers design a chip with specialized software called electronic design automation, or EDA.[5] The software works out where billions of tiny switches go and how wires connect them.[6] Engineers test the design in simulation before anything is built.[7] The finished design then goes to a factory, often a contract manufacturer called a foundry.[1] Many chip companies, including NVIDIA, design chips but do not make them.[8]

    Designers write the logic in a hardware description language such as Verilog or VHDL. Logic synthesis then turns it into a gate-level netlist.[9] Place-and-route tools set the physical location of billions of gates and the metal routing between them.[6] Simulation and verification check behavior before logical and physical implementation.[7] The finalized design goes to a fab. Fabless firms such as NVIDIA use foundries like TSMC and Samsung.[8]

    Wafer fabrication

    Chips start as thin discs called wafers, cut from a block of extremely pure silicon.[10] The factory adds very thin layers of material to the wafer.[11] It then prints a pattern, etches away what is not needed, and adjusts how parts of the pattern conduct electricity.[12][13] This cycle repeats hundreds of times to build up the chip.[14]

    Wafers are sliced from an ingot of 99.99% pure silicon.[10] Each layer begins with deposition of conducting, insulating or semiconducting thin films.[11] After lithography, etch removes the degraded resist to reveal the pattern.[12] Ion implantation then tunes the conductivity of selected regions.[13] The sequence runs hundreds of times per chip.[14] Transistor structure is changing at the leading edge. TSMC’s N2 process, in volume production since the fourth quarter of 2025, is its first with nanosheet transistors.[15] Intel 18A combines RibbonFET gate-all-around transistors with PowerVia backside power delivery.[16] Why these changes became necessary is covered in why chip scaling slowed: Dennard scaling, which kept power density roughly constant as transistors shrank, broke down around 2005.[17][18]

    Lithography

    Lithography works a bit like photography. The wafer is coated with a light-sensitive layer. Light shines through a stencil, called a reticle, and changes the coating where it lands, copying the pattern.[19][20] Shorter wavelengths of light can print smaller details.[4] The most advanced machines use extreme ultraviolet (EUV) light, and ASML describes the technology as unique to ASML.[21]

    DUV scanners use 248 nm krypton-fluoride or 193 nm argon-fluoride excimer lasers.[22] EUV uses 13.5 nm light, more than 14 times shorter.[3] The light comes from molten tin droplets about 25 microns wide. A laser pulse flattens each droplet, and a stronger pulse vaporizes it into a plasma that emits EUV.[23] ASML says its EUV systems print the most intricate layers at 13 nm resolution, which DUV cannot reach.[21] Exposure chemically changes the photoresist, copying the reticle pattern onto the wafer.[19]

    Packaging

    A finished wafer holds many chips. A diamond saw cuts it into individual pieces called dies.[2] For AI processors, the die is often packaged next to stacks of fast memory on a shared base, so data moves quickly between them.[24]

    Wafers are diced into individual dies.[2] AI accelerators often use 2.5D packaging such as TSMC’s CoWoS. It mounts logic dies and multiple HBM stacks on a silicon interposer that can exceed twice the reticle size, about 1,700 mm².[24] NVIDIA uses CoWoS to package its chips.[25] Combining several dies in one package is known as the chiplet approach. Intel’s Foveros, for example, stacks multiple chiplets into one system-on-chip.[26] Hybrid bonding joins stacked dies with direct copper-to-copper connections instead of solder bumps.[27] Packaging memory close to logic matters because memory bandwidth has become a main bottleneck for AI workloads, the memory wall.[28]

    Putting it together

    The stages are often done by different companies. A chip designer uses EDA software from tool vendors, and a foundry fabricates the wafers.[5][8] The foundry relies on lithography machines, and the most advanced of these, EUV scanners, come from ASML.[21] Memory for AI accelerators comes from separate memory makers and is joined to the processor in the package.[24] Export rules reach several of these hand-offs. US controls cover advanced computing chips, high-bandwidth memory and some chipmaking equipment.[29] For more on who supplies each step, see the TSMC and ASML pages.

    Questions readers ask

    Why does lithography use such short wavelengths of light?

    The shorter the wavelength, the smaller the features lithography can print. EUV light, at 13.5 nm, is more than 14 times shorter than DUV light.[4][3]

    Do chip companies like NVIDIA make their own chips?

    No. NVIDIA follows a fabless model and uses foundries such as TSMC and Samsung to make its chips.[8]

    How many times does a wafer go through the manufacturing steps?

    According to ASML, a chip goes through the deposition, lithography, etch and implantation cycle hundreds of times.[14]

    What is advanced packaging?

    Packaging techniques such as TSMC's CoWoS place processor chips and several high-bandwidth memory stacks side by side on a shared silicon interposer.[24]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      A finished chip design is sent to a fabrication facility, often a contract manufacturer called a foundry. confirmedas of 2026-10-10

    2. [2]

      Finished wafers are cut with a diamond saw into individual chips called dies. confirmedas of 2026-10-10

    3. [3]

      EUV lithography uses light with a wavelength of 13.5 nm, more than 14 times shorter than DUV light. confirmedas of 2026-10-10

    4. [4]

      The shorter the wavelength of light, the smaller the features lithography can print. confirmedas of 2026-10-10

    5. [5]

      Electronic design automation (EDA) is the set of software and hardware tools engineers use to design chips. confirmedas of 2026-10-10

    6. [6]

      Place-and-route tools decide where billions of logic gates sit on the chip and how metal wires connect them. confirmedas of 2026-10-10

    7. [7]

      Simulation and verification tools test whether a design behaves as intended before it is physically built. confirmedas of 2026-10-10

    8. [8]

      NVIDIA follows a fabless model, using foundries such as TSMC and Samsung to make its chips. confirmedas of 2026-02-25

    9. [9]

      Chip designers describe a design in a hardware description language such as Verilog or VHDL, and logic synthesis tools turn it into a gate-level netlist. confirmedas of 2026-10-10

    10. [10]

      Wafers are sliced from an ingot of 99.99% pure silicon. confirmedas of 2026-10-10

    11. [11]

      Thin films of conducting, insulating or semiconducting material are deposited on the wafer before a layer is printed. confirmedas of 2026-10-10

    12. [12]

      In the etch step, degraded resist is removed to reveal the intended pattern. confirmedas of 2026-10-10

    13. [13]

      The wafer may be bombarded with ions to tune the electrical conductivity of parts of the pattern. confirmedas of 2026-10-10

    14. [14]

      A chip goes through the deposition-to-implantation cycle hundreds of times before it is finished. confirmedas of 2026-10-10

    15. [15]

      TSMC's 2nm (N2) process, its first with nanosheet transistors, entered volume production in the fourth quarter of 2025. confirmedas of 2026-10-10

    16. [16]

      Intel 18A uses RibbonFET, a gate-all-around transistor in which the gate fully surrounds the channel, and PowerVia, which moves power delivery to the back of the die. confirmedas of 2026-10-10

      • Intel 18A · Intel Foundry (retrieved 2026-10-10)
      • Intel 18A · Intel Foundry (retrieved 2026-10-10)
    17. [17]

      For decades Dennard scaling kept chip power density roughly constant as transistors shrank, sustaining Moore's-law performance gains. confirmedas of 2026-10-10

    18. [18]

      Dennard scaling broke down around 2005, creating a "power wall" that limited further increases in processor clock frequency. confirmedas of 2026-10-10

    19. [19]

      The wafer is coated with a light-sensitive layer called photoresist, which changes chemically where light hits it, copying the pattern from the reticle. confirmedas of 2026-10-10

    20. [20]

      In lithography, deep ultraviolet (DUV) or extreme ultraviolet (EUV) light is projected through a reticle, which holds the pattern to be printed, onto the wafer. confirmedas of 2026-10-10

    21. [21]

      ASML describes EUV as unique to ASML; its EUV systems print the most intricate chip layers at a resolution of 13 nm, which DUV cannot reach. confirmedas of 2026-10-10

    22. [22]

      DUV lithography uses krypton-fluoride lasers at 248 nm and argon-fluoride lasers at 193 nm. confirmedas of 2026-10-10

    23. [23]

      EUV light is made by hitting molten tin droplets about 25 microns wide with two laser pulses, creating a plasma that emits EUV light. confirmedas of 2026-10-10

    24. [24]

      TSMC's CoWoS packaging places processor chips and multiple high-bandwidth memory (HBM) stacks on a shared interposer, which can exceed twice the reticle size (about 1,700 mm²). confirmedas of 2026-10-10

      • CoWoS · TSMC · Overview; the page renders the unit as mm with a superscript 2 (retrieved 2026-10-10)
      • CoWoS · TSMC (retrieved 2026-10-10)
    25. [25]

      NVIDIA uses CoWoS technology to package its chips. confirmedas of 2026-02-25

    26. [26]

      Intel's Foveros is an advanced packaging and 3D stacking technology that integrates multiple chiplets into one system-on-chip, and Panther Lake uses it. confirmedas of 2025-10-09

    27. [27]

      Hybrid bonding joins two chips with dense, direct copper-to-copper connections instead of solder bumps; the copper pads are surrounded by insulating oxide and slightly recessed from its surface. confirmedas of 2024-08-11

    28. [28]

      The same analysis argues that memory bandwidth, rather than compute, has become the primary bottleneck for AI workloads, especially when serving models. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    29. [29]

      A BIS rule effective December 2, 2024 added controls on certain semiconductor manufacturing equipment and high-bandwidth memory, and created new foreign direct product rules aimed at advanced-node chip production. confirmedas of 2024-12-05

    Revision history (2)
    1. Page created.
    2. Refresh: fixed three excerpts to verbatim quotes (Synopsys, ASML, TSMC CoWoS); linked the transistor, backside-power, chiplet and hybrid-bonding pages from the computing-hardware field.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Apr 10, 2027.

    Cite this page

    "How advanced chips are made." ContentLora, updated Oct 10, 2026. https://contentlora.com/explain/how-chips-are-made

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