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    Hybrid bonding

    Also known as Cu-Cu hybrid bonding, direct bond interconnect, bumpless bonding

    Hybrid bonding joins two chips face to face with dense, direct copper connections set in insulating oxide, replacing solder microbumps.[1] Production parts had connections about 9 micrometres apart by 2024, while imec demonstrated 400 nanometres in research, making it a key tool for 3D chiplet stacking.[2][3]

    Editor reviewedUpdated Next-gen computing hardwareSemiconductors
    Key facts

    Hybrid bonding is a way of stacking chips so that they connect through dense, direct copper-to-copper joints rather than through solder. It is called “hybrid” because two materials bond at once: the copper pads and the insulating oxide around them.[1] It is one of the main enablers of 3D chiplet designs.[4]

    How it works

    Think of two Lego plates pressed together, except the studs are microscopic copper pads and there is no glue. Each chip’s surface is polished almost perfectly flat, with copper pads set into a glass-like layer. When the two surfaces are pressed together and heated, the glass layers stick and the copper pads fuse, forming a dense grid of electrical connections.[1][5]

    Copper pads are formed on each die face, surrounded by oxide and slightly recessed from it.[1] During bonding the copper must expand by a tightly controlled amount: too little and the pads do not fuse, too much and the wafers are pushed apart.[6] Chemical-mechanical planarization must remove nanometre-scale bulges, since slight warping can break dense connections.[5] The faces are pressed together so the recessed pads align and then slowly heated, so the copper expands across the gap and fuses.[7] That final anneal typically runs at around 300 °C and can take hours, which researchers are trying to cut.[8]

    Why pitch matters

    The closer the connections, the more data can pass between stacked chips for the same area and energy. Solder microbumps, the previous approach, have pitches in the tens of micrometres. By 2024, hybrid-bonded chips in production had connections about 9 micrometres apart.[2] In research, imec has shown 400-nanometre pitch for wafer-to-wafer bonding and 2-micrometre pitch for chip-on-wafer bonding.[3] For comparison, the UCIe Consortium says stacked chiplets can connect at pitches as low as 1 micrometre, though 5-25 micrometres is currently more common.[9] Research presented in 2024 pointed toward about 7 million links per square millimetre.[10]

    Where it is used

    IEEE Spectrum reported in 2024 that AMD uses chip-on-wafer hybrid bonding to join compute cores and cache memory in its advanced processors and AI accelerators, that wafer-to-wafer bonding is mature partly because of its use in camera chips, and that researchers see it as critical for future high-bandwidth memory (HBM).[4]

    HBM shows the technique is not yet universal. SK hynix said it stacked its first HBM4 with its established Advanced MR-MUF process, which fills the gaps between dies with a liquid protective material, to minimise mass-production risk.[11] Samsung’s HBM4, shipping since February 2026, sits on a 4nm logic base die.[12]

    The reason for the interest is a change in how chips improve. Intel engineers describe system technology co-optimization, in which cache, input/output and logic are each made on the best process and then joined, which only works with dense chip-to-chip links.[13] Yole Group forecast in 2024 that advanced packaging would more than triple to US$38 billion by 2029, with hybrid bonding about half of it.[14] Dense vertical links are one answer to the data-movement problem that limits AI chips.[15]

    Hybrid bonding and the memory wall

    Dense vertical links matter because AI chips are increasingly limited by how fast data reaches them: one analysis found compute growing about 3.0x every two years against 1.6x for DRAM bandwidth.[16] Stacking memory or cache directly on logic shortens those paths. For the side-by-side alternative, 2.5D packaging, the UCIe Consortium lists 25-55 micrometre pitches, several times coarser than production hybrid bonding.[9][2] Packaging capacity for AI chips remains tight: TSMC’s CoWoS supply gap was expected to narrow only to about 10% by the end of 2026.[17] See AI chip supply concentration for the wider bottleneck.

    Challenges

    The main obstacles are manufacturing ones. Surfaces must be extremely flat and clean, and the copper’s expansion must be controlled to within nanometres.[5][6] Researchers are also trying to shorten the hours-long, high-temperature anneal.[8] Public data on hybrid-bonding yields in high-volume products is limited.[2]

    Questions readers ask

    How is hybrid bonding different from solder bumps?

    Solder microbumps have pitches in the tens of micrometres; hybrid-bonded chips in production had connections about 9 micrometres apart by 2024.[2]

    Where is hybrid bonding used?

    In AMD processors and AI accelerators, in camera image sensors, and increasingly in high-bandwidth memory stacks.[4]

    Is HBM4 made with hybrid bonding?

    Not necessarily. SK hynix said it used its established Advanced MR-MUF stacking process for HBM4, although researchers see chip-on-wafer hybrid bonding as critical for future HBM.[11][4]

    What makes it hard?

    Surfaces must be extremely flat; engineers polish away the last few nanometres of oxide because slight bulges or warping can break connections.[5]

    Sources

    Each numbered claim is a statement we checked against the sources listed with it. Status shows how well established it is.

    1. [1]

      Hybrid bonding joins two chips with dense, direct copper-to-copper connections instead of solder bumps; the copper pads are surrounded by insulating oxide and slightly recessed from its surface. confirmedas of 2024-08-11

    2. [2]

      As of 2024, hybrid-bonded 3D chips in production had connections about 9 micrometres apart, versus tens of micrometres for the solder microbumps they replace. confirmedas of 2024-08-11

    3. [3]

      imec has demonstrated wafer-to-wafer hybrid bonding with a 400-nanometre pitch, and 2-micrometre pitch for chip-on-wafer bonding. confirmedas of 2024-08-11

    4. [4]

      Hybrid bonding is used in AMD processors and AI accelerators, in camera image sensors, and is being applied to high-bandwidth memory stacks. confirmedas of 2024-08-11

    5. [5]

      Hybrid bonding requires extreme surface flatness; engineers polish away the last few nanometres of oxide because slight bulges or warping can break dense connections. confirmedas of 2024-08-11

    6. [6]

      In hybrid bonding the copper pads must expand by a precisely controlled amount when heated; too little and they do not fuse, too much and the wafers are pushed apart. confirmedas of 2024-08-11

    7. [7]

      In hybrid bonding the chips are pressed face-to-face so their recessed copper pads align, forming weak initial bonds between the oxide surfaces, and then slowly heated so the copper expands across the gap and fuses. confirmedas of 2024-08-11

    8. [8]

      The final hybrid-bonding anneal typically runs at around 300 °C and can take hours, and researchers are trying to lower the temperature and shorten the process. confirmedas of 2024-08-11

    9. [9]

      According to the UCIe Consortium, standard packages connect chiplets at 100-150 micrometre pitches and advanced packages at 25-55 micrometres, while stacked chiplets can connect at pitches as low as 1 micrometre, with 5-25 micrometres currently more common. confirmedas of 2025-04-11

    10. [10]

      Research presented at ECTC 2024 pointed toward a record density of about 7 million links per square millimetre between stacked chips. reportedas of 2024-08-11

    11. [11]

      SK hynix said it used its market-proven Advanced MR-MUF stacking process for HBM4, which injects a liquid protective material between stacked chips and hardens it, to minimise mass-production risk. confirmedas of 2025-09-12

    12. [12]

      On February 12, 2026 Samsung said it had begun mass production of HBM4 and shipped commercial products, running at 11.7Gbps (up to 13Gbps) with its sixth-generation 10nm-class (1c) DRAM and a 4nm logic base die. confirmedas of 2026-02-12

    13. [13]

      Intel engineers describe current progress as system technology co-optimization, in which functions such as cache, input/output and logic are each made with the best process and then joined, which requires dense chip-to-chip connections. confirmedas of 2024-08-11

    14. [14]

      Yole Group projected in 2024 that the advanced-packaging market would more than triple to US$38 billion by 2029, with hybrid bonding making up about half of it by then. reportedas of 2024-08-11· forecast

    15. [15]

      The same analysis argues that memory bandwidth, rather than compute, has become the primary bottleneck for AI workloads, especially when serving models. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    16. [16]

      A 2024 analysis found peak server hardware FLOPS grew about 3.0x every two years, while DRAM bandwidth grew about 1.6x and interconnect bandwidth about 1.4x over the same period. confirmedas of 2024-03-21

      • AI and Memory Wall · arXiv (published in IEEE Micro) · 2024-03-21 · Abstract (retrieved 2026-10-10)
    17. [17]

      Institutional investors cited by Taiwan's Economic Daily News expected the CoWoS supply-demand gap to narrow from about 20% to about 10% by the end of 2026. reportedas of 2026-06-15· forecast

    Revision history (2)
    1. Page created.
    2. Added the bonding process steps, density record, anneal limits, market forecast and HBM4 stacking context; corrected the 3D pitch range.

    Created Oct 10, 2026. Last reviewed by an editor on Oct 10, 2026. Next scheduled review: Jan 10, 2027.

    Cite this page

    "Hybrid bonding." ContentLora, updated Oct 10, 2026. https://contentlora.com/wiki/hybrid-bonding

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